鎖相環之外文翻譯畢業論文-全文預覽

　　

【正文】 I Semiconductor’s latest mixedsignal technology offers digital and analog integration capabilities on the same design platform. The I3T technology family is based on standard CMOS ?181。s too close to the pace car, he will slow down. The result is all the race cars lock on to the phase of the pace car. The cars travel around the track in a tight group that is a small fraction of a lap.Clock analogyPhase can be proportional to time, so a phase difference can be a time difference. Clocks are, with varying degrees of accuracy, phaselocked (timelocked) to a master clock.Left on its own, each clock will mark time at slightly different rates. A wall clock, for example, might be fast by a few seconds per hour pared to the reference clock at NIST. Over time, that time difference would bee substantial.To keep his clock in synch, each week the owner pares the time on his wall clock to a more accurate clock (a phase parison), and he resets his clock. Left alone, the wall clock will continue to diverge from the reference clock at the same few seconds per hour rate.Some clocks have a timing adjustment (a fastslow control). When the owner pared his wall clock39。 in space munications for coherent demodulation and threshold extension, bit synchronization, and symbol synchronization. Phaselocked loops can also be used to demodulate frequencymodulated signals. In radio transmitters, a PLL is used to synthesize new frequencies which are a multiple of a reference frequency, with the same stability as the reference frequency.Other applications include:˙Demodulation of both FM and AM signals˙Recovery of small signals that otherwise would be lost in noise (lockin amplifier)˙Recovery of clock timing information from a data stream such as from a disk drive˙Clock multipliers in microprocessors that allow internal processor elements to run faster than external connections, while maintaining precise timing relationships˙DTMF decoders, modems, and other tone decoders, for remote control and telemunicationsClock recoverySome data streams, especially highspeed serial data streams (such as the raw stream of data from the magnetic head of a disk drive), are sent without an acpanying clock. The receiver generates a clock from an approximate frequency reference, and then phasealigns to the transitions in the data stream with a PLL. This process is referred to as clock recovery. In order for this scheme to work, the data stream must have a transition frequently enough to correct any drift in the PLL39。s feedback input. The function of the PLL is to pare the distributed clock to the ining reference clock, and vary the phase and frequency of its output until the reference and feedback clocks are phase and frequency matched.PLLs are ubiquitous—they tune clocks in systems several feet across, as well as clocks in small portions of individual chips. Sometimes the reference clock may not actually be a pure clock at all, but rather a data stream with enough transitions that the PLL is able to recover a regular clock from that stream. Sometimes the reference clock is the same frequenc。MHz) up to the operating frequency of the processor. The multiplication factor can be quite large in cases where the operating frequency is multiple gigahertz and the reference crystal is just tens or hundreds of megahertz.Spread spectrumAll electronic systems emit some unwanted radio frequency energy. Various regulatory agencies (such as the FCC in the United States) put limits on the emitted energy and any interference caused by it. The emitted noise generally appears at sharp spectral peaks (usually at the operating frequency of the device, and a few harmonics). A system designer can use a spreadspectrum PLL to reduce interference with highQ receivers by spreading the energy over a larger portion of the spectrum. For example, by changing the operating frequency up and down by a small amount (about 1%), a device running at hundreds of megahertz can spread its interference evenly over a few megahertz of spectrum, which drastically reduces the amount of noise seen on broadcast FM radio channels, which have a bandwidth of several tens of kilohertz.Clock distributionTypically, the reference clock enters the chip and drives a phase locked loop (PLL), which then drives the system39。s notion of a second would agree with the reference time (within the wall clock39。 effectively creating onchip “pockets” where noise and power supply parameters are carefully controlled.On top of its protection skills, the deep trench technology also helps to minimize die area by allowing dense packing of highvoltage analog pockets with lowvoltage regions. You can obtain improvements in die area of 10 to 60 percent over designs that use standard junction isolation techniques.As mentioned earlier, the reason that system designers are using deep submicron technologies in those markets is often linked to the availability of devices in those technologies, not the plexity of the application itself. The plexity can be handled in many cases by an 8bit microcontroller, or 32bit for highend applications. Products such as the ?181。由于最初的振蕩器頻率可能遠遠高于參考頻率，實用鑒相器也可能響應頻率的差異，所以增加允許輸入的鎖定范圍。 振蕩器產生一個周期的輸出信號。這輸入被稱為參考輸入。錯誤信號通過低通濾波并用來驅動創建輸出相位的VCO。頻率合成器制造商包括ADI導體和德州儀器。頻率合成在數字無線通信系統（GSM，CDMA等）中，鎖相環為傳輸過程中上轉換和接收過程中下轉提供本地振蕩器。相位噪聲是觀測鎖相環的抖動的另一種類型，該抖動由振蕩器自身和使用的振蕩器頻率控制電路元件引起的。減少抖動和噪聲鎖相環的一個可取性質是參考和??反饋時鐘邊沿非常密切的協調起來。 鎖相環的功能是比較分布時鐘和傳入的參考時鐘的，相位和輸出頻率一直變化直到基準和反饋時鐘的相位和頻率匹配。例如，通過改變運行頻率的少量升降（約1％），在數百兆赫茲運行的設備可以傳播其干擾，甚至可以越過數兆赫茲的頻譜，從而大大降低了有幾十千赫茲的帶寬的調頻廣播頻道的可見噪音量。擴頻所有電子系統都會產生一些不需要的無線電頻率能量。這種類型的應用程序是鎖相環的一種特殊形式，稱為延遲鎖相環（DLL），是經常用的。因為時鐘在驅動采樣數據的觸發器之前必須接收和放大，這將導致在檢測時鐘邊沿和接收數據窗口之間的有限，過程，溫度和電壓依賴性的延遲。這一過程被稱為時鐘恢復。?微處理器中的時鐘乘法器，允許內部處理器元素的運行速度比外部連接器快，同時 保持精確的時序關系。在無線電發射器，鎖相環用于合成參考頻率整數倍的新頻率，和參考頻率的穩定性相同。高度依賴VCO相位噪聲，鎖相環帶寬等。?瞬態響應：如過沖和穩定時間以達到一定的精度（如50PPM）。性能參數?類型和順序?鎖定范圍：鎖相環的頻率范圍能夠保持鎖定，主要是由VCO的范圍限定的。鎖相環的較早機械版本在1921年用于肖特時鐘同步。當主人將他的掛鐘時間與參考時間相比時，他發現，他的