畢業設計基于fpga的萬年歷設計(留存版)

　　

【正文】 ponents such as flipflop Flip flop) (or other more plete memory blocks. System according to need stylist can be connected by editable the FPGA internal logic, like connecting block a circuit test plate is placed on a chip. A after they leave the finished product FPGA logic blocks and connection can be changed according to the designers, so the FPGA can plete need logical functions. The FPGA in general than ASIC (special integrated chips) speed will slow, unable to perform plex designs, and consume more power. But they also have many advantages such as can quickly finished product, can be modified to correct an error in a programme and cheaper cost. Manufacturers might also offer cheap but editing ability is poor FPGA. Because these chips have more bad of the editable ability, so these design development is in ordinary FPGA pletion, and then on to design transferred to a similar to the chip ASIC. Another method is to use CPLD (plex programmable logic device prepare). Early in the mid 1980s PLD equipment in FPGA has root. CPLD and FPGA includes some relatively large number of programmable logic unit. CPLD logical gate density in a logical units to tens of thousands, and FPGA is usually between in tens of thousands to millions of. The major difference between and FPGA CPLD their system structure. CPLD is a bit of 畢業設計（論文）專用紙 第 頁 15 restrictive structure. This structure by one or more editable results logical groups of the sum of gilead and some relatively low amounts of locking registers. The result is that lack of editing flexibility, but there can be expected to delay time and logic unit link units a high rate of advantages. And there are many connection FPGA is, so although let it unit can be more flexible editor, but the structure are much more plex. CPLD and FPGA another difference is most FPGA contain high levels of builtin module (such as adder and on timemultiplier) and builtin memory. A so the important difference is concerned, many new FPGA support full or part of the system in a configuration. Allow their design with system upgrades or dynamic reconfigured and change. Some FPGA can let equipment edit and part of the normal operation. Other parts continue. By the Logic element Array FPGA LCA (Array) such a Cell questions concept, internal including Configurable Logic module which CLB (Configurable questions) and Output Input module which Output IOB (Input) and internal attachment (Interconnect) three parts. Field programmable gates array (FPGA) is programmable devices. And the traditional logic circuit and the gate array (such as PAL GAL and CPLD device), pared with different structure, the FPGA, FPGA with small lookup table (16 x 1RAM) to realize the bination of logic, each lookup table connected to a D flipflop input and trigger again drive other logic circuit or driver I/O, which constitutes the assembly logic functions can be realized and realize the basic logic sequential logical function module, these module unit by using metal connection between interconnected or connected to the I/O modules. The logic is through FPGA inward. Current main FPGA is still based on lookup table technology, has far exceeded the previous version of the basic performance, and integrate the mon functions (such as RAM, clock management and the hardcore (DSP) ASIC type) module. The FPGA chip partially pleted by 7 to Lord, respectively: programmable input/output unit, basic programmable logic unit, plete clock management, embedded pieces type RAM, rich wiring resources, embedded bottom function units and inline dedicated hardware modules. 畢業設計（論文）專用紙 第 頁 16 The function of each module are as follows: 1. Programmable input/output unit (IOB) Programmable input/output unit referred to as I/O unit, is the interface with external circuit chip, plete different part electrical characteristics of input/output signal driver and matching requirements, its beckoned structure shown as shown in figure 12. The I/O within the FPGA in groups, each of classification can be independently support different I/O standards. Through the flexible configuration software can fit different electrical standards and I/O physical properties, can adjust the drive current size, can change, pulldown resistor. At present, the frequency of I/O port more and more is also high, some highend FPGA technology can support by DDR 2Gbps registers as the data rate. External input signal can through the storage unit IOB module input into the FPGA interior, may also enter the FPGA internal. When external input signal after IOB module ? the storage unit. To facilitate the management and adapt to a variety of electric equipment standard, FPGA IOB was divided into the several group (the somebody), each by its interface standard somebody VCCO decision, a interface voltage somebody there can be only one of VCCO, but different VCCO can differ to somebody. Only the same electrical standard ports to connect together, VCCO voltage is the basic condition of interface standards. 2. Configurable logic block (CLB) CLB is the basic logic unit within the FPGA. The actual number of CLB of the device and the characteristic will depend on different and different, but each CLB contains a configurable, the matrix switching matrix by four or six input, some selection circuits (multiplexing machines etc) and trigger position. A switching matrix is highly flexible, open to configuration so that treatment binations logic, the shift register or RAM. Xilinx FPGA device in the pany, by multiple (CLB is generally four or 2) the same Slice and additional logic structure, as shown in figure 13 below. Each CLB module can not only used to implement the binational logic, temporal logic, also can be configured to 畢業設計（論文）專用紙 第 頁 17 distributed RAM and distri