電氣專業畢業設計外文文獻與中文翻譯-文庫吧在線文庫

　　

【正文】 g the low power mode to reduce power consumption. At this time, VDD1 V, VDD2 volts to 1. Case four: audio / video encoding 540 mW (nonDPLL power and IO). In that case, we capture and encode audio (AACe +, 48 kHz, 32k bps stereo), video capture and encoding ( VGA resolution, 20 frames per second, Mbsp), audio and video are preserved, At the same time to display video. In the configuration, ARM operates at 500 MHz, DSP operating frequency is 360 MHz, VDD1 V, VDD2 to volts. In addition, the subsystemchip camera sensor can capture video from an external input, multichannel buffered serial port input PCM audio capture, IVA implementation of audio and video encoding, encoding data stored in the multimedia card, which makes video display subsystem cycle, and video sent to the LCD and TV output interface. Implementation of power management In order to achieve the full flexibility of power management, DSP processor chip power device reset and clock management (PRCM). OMAP3530 processor function module is divided into 18 power domains, each domain has its own power switch. PRCM can switch all the power domain, but many power supplies may also be usercontrolled domain. In addition, each power domain can be based on whether the logic and memory power, and the clock is in working condition and enter the four states: the work of state, nonworking condition, and maintain on or off. On the ARM and DSP devices, the abovementioned state regulators usually require auxiliary. Many of the market regulators to meet these requirements can, of course, need to meet the processor39。s performance in the established frequency to follow a certain request distribution. Some devices (the socalled hot devices) pared to other devices (the socalled cold devices), the lower voltage to achieve a given frequency, and this is the role of the principle of AVS Processor sensors to their own performance level, and adjust the supply voltage. AVS dedicated hardware chip feedback loop can be implemented without processor intervention voltage level dynamic optimization to meet the needs of the process, temperature and silicon attenuation difference caused by the requirements (Figure 1). Figure 1Given the performance of the distribution of a typical processor. Here39。利用 DVFS 技術，可根據應用的性能需求通過軟件來降低時鐘速度和電壓。為了在最佳功耗情況下實現必需的功能性，我們可將 VDD1 降至 伏特，而不使用最高 伏特的電壓，以確保 600 MHz 的工作頻率。自適應電壓縮放 (AVS) 技術采用反饋環路相應調節供電電壓，確保各器件運行在特定處理任務所需的頻率上軟件可在工作中為每個 OPP 設置 AVS 硬件，而控制算法則通過 I2C 總線向外部穩壓器發送指令，以逐步降低適當穩壓器的輸出，直至處理器剛好超過目標頻率的要求為止。要實現這一目的，我們可應用靜態漏電管理 (SLM) 技術，啟動待機或器件關閉模式。處理器內部不保存存儲器或邏輯。最后，如果用戶打開媒體播放器但數小時或數天都不使用，其會通過 SLM 技術自動使器件進入關閉模式。案例二：待機模式 — 7 mW。就系統配置而言，DSP 的工作頻率為 90 MHz，在無需處理周期時進入低功耗模式以降低功耗。PRCM 可開關所有電源域，但許多電源域也可由用戶控制。圖 3高級穩壓器芯片集成了多個開關穩壓器與低壓降線性穩壓器，因而可滿足 OMAP35x 處理器的電壓域要求13。就 ARM 與 DSP 器件而言，上述狀態通常需要輔助穩壓器。案例四：音頻/視頻編碼 — 540 mW(不含 DPLL 與 IO功耗)。所有邏輯和存儲器將保留。在以下案例中，除有特別說明，否則我們一概不采用 TI 的 AVS/SmartReflex 技術。經后喚醒復位后，微處理器單元 (MPU) 會啟動用戶定義的功能，SDRAM 控制器配置從高速暫存存儲器 (SPM) 中恢復。利用 SLM 技術，喚醒時間大大快于冷啟動速度，因為程序已經載入到了外部存儲器，用戶無需等待操作系統 (OS) 完全重新啟動。但是，如果系統中插入了采用 AVS 技術的“熱”器件，那么片上反饋機制就會自動將 ARM 的電壓降至 伏特或更低(圖 1 中的 V2 上方)。該技術與所有處理器都