基于i2c總線(xiàn)的數(shù)據(jù)采集系統(tǒng)自動(dòng)化專(zhuān)業(yè)畢業(yè)設(shè)計(jì)畢業(yè)論(編輯修改稿)

　

【文章內(nèi)容簡(jiǎn)介】 C 總線(xiàn)是多主機(jī)總線(xiàn)，可以有兩個(gè)或更多的能夠控制總線(xiàn)的器件與總線(xiàn)連接；同時(shí) I2C 總線(xiàn)還具有仲裁功能，當(dāng)一個(gè)以上的主器件同時(shí)試圖控制總線(xiàn)時(shí)，只允許一個(gè)有效，從而保證數(shù)據(jù)不被破壞 .I2C 總線(xiàn)的尋址采用純軟件的尋址方法，無(wú)需片選線(xiàn)的連接，這樣就簡(jiǎn)少了總線(xiàn)數(shù)量。主機(jī)在發(fā)送完啟動(dòng)信號(hào)后，立即發(fā)送尋址字節(jié)來(lái)尋址被控器件，并規(guī)定數(shù)據(jù)傳送方向。尋址字節(jié)由 7 位從機(jī)地址（ D7～ D1）和 1 位方向位（ D0， 0/1，讀 /寫(xiě)）組成。 當(dāng)主機(jī)發(fā)送尋址字節(jié)時(shí)，總線(xiàn)上所有器件都將該尋址字節(jié)中的高 7 位地址與自己器件的地址比較，若兩者相同，則該器件認(rèn)為被主機(jī)尋址，并根據(jù)讀 /寫(xiě)位確定是從發(fā) 送器還是從接收器。 I2C 總線(xiàn)具有 多重主控能力 ，這就意味著可以允許多個(gè)作為主控器的電路模塊（具有 I2C 總線(xiàn)接口的單片機(jī)）去搶總線(xiàn)。所以 掛接在 I2C 總線(xiàn)上的集成電路模塊的發(fā)送器/接收器可以根據(jù)不同的工作狀態(tài)反為主 控發(fā)送器，主控接受器，被控發(fā)送 器， 被控接收器。顯然，具有 I2C 總線(xiàn)接口的單片機(jī)可以工作在上述 4 種工作狀態(tài)中的任一狀態(tài)，而帶有 I2C 總線(xiàn)接口的存儲(chǔ)器 。 I2C 只有兩根雙向的信號(hào)線(xiàn)，一根是數(shù)據(jù)線(xiàn) SDA，另一根是時(shí)鐘線(xiàn) SCL。所有連接到I2C 總線(xiàn)上器件的數(shù)據(jù)線(xiàn)都是接到 SDA 線(xiàn)上，各器件的時(shí)鐘線(xiàn)均接到 SCL 線(xiàn)上。每個(gè)連接到總線(xiàn)的器件都可以通過(guò)唯一的地址和 一直存在的簡(jiǎn)單的主機(jī)關(guān)系軟件設(shè)定地址，主機(jī)可以作為主機(jī)發(fā)送器或主機(jī)接收器。 I2C 是一個(gè)真正的多主機(jī)總線(xiàn)，如果兩個(gè)或更多主機(jī)同時(shí)初始化，數(shù)據(jù)傳輸可以通過(guò)沖突檢測(cè)和仲裁防止數(shù)據(jù)被破壞。串行的 8 位雙向數(shù)據(jù)傳輸位速率在標(biāo)準(zhǔn)模式下可達(dá) 100bit/s，快速模式下可達(dá) 400bit/s，高速模式下可達(dá) 。連接到相同總線(xiàn)的 IC 數(shù)量只受到總線(xiàn)的最大電容 400pF 限制。 本課題是基于 I2C 總線(xiàn)的數(shù)據(jù)采集系統(tǒng)，要求單片機(jī)與具有 I2C 總線(xiàn)的 24C02 存儲(chǔ)基于 I2C 總線(xiàn)的數(shù)據(jù)采集系統(tǒng) 16 器件進(jìn)行讀寫(xiě)操作，本課題的思想是用 4*4 的開(kāi)關(guān)組成的鍵盤(pán)或撥碼 開(kāi)關(guān)作為外部輸入，存儲(chǔ)在 24c02 中，再?gòu)?24C02 中取出數(shù)據(jù)同在單片機(jī)，并在數(shù)碼管上顯示出來(lái)。由此完成 I2C 總線(xiàn)的數(shù)據(jù)采集系統(tǒng)。 Abstract I2Cbus is a th highperformance serial bus of automatic addressing, highspeed device synchronization and arbitration functions . It can achieve fullduplex data transmission perfect, and is the use of a variety of bus signal lines in the least number. I2C bus has only two signal lines: data line SDA and the clock line SCL. All access to I2Cbus system with I2C bus interface devices, in line with I2Cbus electrical specification features, It just need all the nodes on the bus I2C serial data line SDA and SCL clock line respectively, and the SCL and SDA bus can be connected. Power of each node can be different, but to be mon ground, the other SDA and SCL are connected to the pullup resistor required. When performing data transfer, start the data transmission and generates a device known as the master clock signal devices。 be any device that can be addressed as a slave。 send data to the device on the bus as a transmitter。 receive data from the bus The device known as the receiver. I2C bus is a multimaster bus, can have two or more devices to control the bus and bus connections。 The same I2C bus also has an arbitration function, when more than one master simultaneously tries to control the bus, only one allow to an effective, ensure that data is not destroyed. I2C bus addressing the addressing method using pure software without chip select line connected, so that lossing number of buses Jane. Master sending the start signal immediately after the address was charged with sending the device address byte, and provides data transfer direction. 7bit address byte from the slave address (D7 ~ D1) and a direction bit (D0, 0 / 1, read / write) form. When the master sends address byte, all the devices on the bus in the highbyte 7bit address and the address of their device pared to if they are the same, the device is believed to be master address, and according to read / Write bits to determine from the transmitter or from the receiver. 基于 I2C 總線(xiàn)的數(shù)據(jù)采集系統(tǒng) 17 I2Cbus with multiple master capability, which means that can allow multiple circuit modules as the master (microcontroller with I2C bus interface) try to steal the bus. So attached to the I2C bus on the integrated circuit module transmitter / receiver according to different working conditions can be counter to the master transmitter, master receiver, was charged with the transmitter, was charged with the receiver. Obviously, with the I2C bus interface of the MCU can operate in the work of the 4 state of any state, and memory with I2C bus interface. Only two bidirectional I2C signal line, one is the data line SDA, the other is the clock line SCL. All devices connected to the I2C bus data line SDA line is received, the device39。s clock line SCL lines are received. Each of the devices connected to the bus can only address and the host has always existed between the simple software configuration address, master can be used as master transmitter or master receiver. I2C is a true multimaster bus, if two or more hosts at the same initialization, data transfer via collision detection and arbitration to prevent data from being destroyed. 8bit bidirectional serial data transmission bit rate in the standard mode, up to 100bit / s, fast mode, up to 400bit / s, highspeed mode, up to / s. IC connected to the same bus number only by the bus capacitance of 400pF the maximum limit. This project is data acquisition system based on the I2Cbus, requiring SCM and 24C02 with I2C bus to read and write memory devices, the idea of this project is posed of 4 * 4 switch DIP switch keyboard or as an external input, is stored in the 24c02 , and then removed from the data with the 24C02 microcontroller, and digital tube display. So I2C bus, which pleted the data acquisition system. 基于 I2C 總線(xiàn)的數(shù)據(jù)采集系統(tǒng) 18 第一章 單片機(jī) 單片機(jī)的簡(jiǎn)單介紹 單片機(jī)是指一個(gè)集成在一塊芯片上的完整計(jì)算機(jī)系統(tǒng)。盡管他的大部分功能集成在一塊小芯片上，但是它具有一個(gè)完整計(jì)算機(jī)所需要的大部分部件： CPU、內(nèi)存、內(nèi)部和外部總線(xiàn)系統(tǒng)，目前大部分還會(huì)具有外存。同時(shí)集成諸如通訊接口、定時(shí)器，實(shí)時(shí)時(shí)鐘等外圍設(shè)備。而現(xiàn)在最強(qiáng)大的單片機(jī)系統(tǒng)甚至可以將聲音、圖像、網(wǎng)絡(luò)、復(fù)雜的輸入輸出系統(tǒng)集成在一塊芯片上。 通道 0 驅(qū)動(dòng)器 通道 2 驅(qū)動(dòng)器R AM 地址鎖存器R AM通道 0 鎖存器通道 2 鎖存器R OM /E P R OMB 寄存器程序地址寄存器緩沖器PC 遞增器程序計(jì)數(shù)器 PC ０驅(qū)動(dòng)器DPT R 指針VCCGNDP1 . 0～ P1 . 7堆棧指針 SPA C CT M P2PSW通道 3 鎖存器通道 1 鎖存器通道 1 驅(qū)動(dòng)器 通道 3 驅(qū)動(dòng)器T M P1S C ON T M ODP C ON T C ONT L 0 T H1T H0 T L 1IES B UF ( T X/R X) IP中斷、串行口和定時(shí)器邏輯振蕩器P3 . 0～ P3 . 7R S TEAAL EP S E NXT A L2XT A L1AL U( + 5 V)指令寄存器定時(shí)和控制邏輯指令譯碼器圖 2 2 M C S 51 片內(nèi)總體結(jié)構(gòu)框圖通道 驅(qū)動(dòng)器 通道 驅(qū)動(dòng)器地址鎖存器鎖存器鎖存器寄存器程序地址寄存器緩沖器遞增器程序計(jì)數(shù)器 ０驅(qū)動(dòng)器指針～堆棧指針通道 鎖存器通道 鎖存器通道 驅(qū)動(dòng)器 通道 驅(qū)動(dòng)器中斷、串行口和定時(shí)器邏輯振蕩器振蕩器～EA指令寄存器定時(shí)和控制邏輯指令譯碼器指令寄存器定時(shí)和控制邏輯指令譯碼器圖 片內(nèi)總體結(jié)構(gòu)框圖 圖 11 MCS51 片內(nèi)總體結(jié)構(gòu)框圖 基于 I2C 總線(xiàn)的數(shù)據(jù)采集系統(tǒng) 19 單片機(jī)的特點(diǎn) 高 ，體積小，可靠性 高。 單片機(jī)將各 功能部件集成在一塊晶體芯片上，集成度很高。 其 內(nèi)部布線(xiàn)很短， 因此 其抗工業(yè)噪音性能優(yōu)于一般通用的 CPU。 另外，其體積小，對(duì)于強(qiáng)磁場(chǎng)環(huán)境易于采取屏蔽措施，適合在惡劣環(huán)境下工作。 。 為了滿(mǎn)足對(duì)對(duì)象的控制要求，單片機(jī)的指令系統(tǒng)均有極豐富的條件 :分支轉(zhuǎn)移能力， I/O 口的邏輯操作及位處理能力，適用于專(zhuān)門(mén)的控制功能。 。 片內(nèi)具有計(jì)算機(jī)正常運(yùn)行所必需的部件。芯片外部有許多供擴(kuò)展用的三總線(xiàn)及并行、串行輸入 /輸出管腳，很容易構(gòu)成各種規(guī)模的計(jì)算機(jī)應(yīng)用系統(tǒng)。 I2C（ InterIntegrated Circuit）及 SPI(Serial Peripheral Interface)等串行總線(xiàn)方式，進(jìn)一步縮小了體積，簡(jiǎn)化了結(jié)構(gòu)。 ，低功耗，便于生產(chǎn)便攜式產(chǎn)品 。 單片機(jī)的應(yīng)用領(lǐng)域 辦公自動(dòng)化設(shè)備 中的應(yīng)用 、尖端武器等領(lǐng)域 用于 汽車(chē)電子產(chǎn)品 基于 I2C 總線(xiàn)的數(shù)據(jù)采集系統(tǒng) 20 AT80C51 AT80C51 單片機(jī)簡(jiǎn)介 AT89C51 是美國(guó) ATMEL 公司生產(chǎn)的低電壓，高性能的 CMOS8 位單片機(jī)片內(nèi) 4Kbytes的可反復(fù)擦寫(xiě)的只讀程序存儲(chǔ)器（ PEROM）和 128bytes 的隨機(jī)存儲(chǔ)器（ RAM），器件采用ATMEL 公司的高密度、非易失存儲(chǔ)技術(shù)生產(chǎn)，兼容標(biāo)準(zhǔn) MCS51 指令系統(tǒng)，片內(nèi)置通用 8位中央處理器（ CPU）和 Flash 存儲(chǔ)單元，功能強(qiáng)大。 AT89C51 單片機(jī)可靈活的應(yīng)用于