基于fpga的vga和hdmi視頻拼接系統設計-資料下載頁

　　

【正文】 .vout_t_height(1239。d768),.vout_K_h(1639。h005a),.vout_K_v(1639。h00c0),///////////mem .mem_clk(phy_clk),.wr_burst_req(ch0_wr_burst_req),.wr_burst_len(ch0_wr_burst_len),.wr_burst_addr(ch0_wr_burst_addr),.wr_burst_data_req(ch0_wr_burst_data_req),.wr_burst_data(ch0_wr_burst_data),.wr_burst_finish(ch0_wr_burst_finish),.rd_burst_req(ch0_rd_burst_req),.rd_burst_len(ch0_rd_burst_len),.rd_burst_addr(ch0_rd_burst_addr),.rd_burst_data_valid(ch0_rd_burst_data_valid),.rd_burst_data(ch0_rd_burst_data),.rd_burst_finish(ch0_rd_burst_finish),36.base_addr(239。d0))。video_pro(.MEM_DATA_BITS(MEM_DATA_BITS))video_pro_m1(.rst_n(139。b1),.vin_pixel_clk(cvbs_in_clkn),.vin_vs(ch0_vs),.vin_f(ch0_f),.vin_pixel_de(ch0_de),.vin_pixel_yc(ch0_yc_data),///////////.vin_scaler_clk(phy_clk),.vin_s_width(1239。d720),.vin_s_height(1239。d576),.clipper_left(1239。d360),.clipper_width(1239。d360),.clipper_top(1239。d0),.clipper_height(1239。d576),.vin_t_width(1239。d360),.vin_t_height(1239。d576),.vin_K_h(1639。h0100), .vin_K_v(1639。h0100),//////////////////////////.vout_pixel_clk(hdmi_out_clk),.vout_vs(hdmi_out_vs),.vout_pixel_rd_req(ch1_vout_rd_req),.vout_pixel_ycbcr(ch1_vout_ycbcr),///////////.vout_scaler_clk(hdmi_out_clk),.vout_s_width(1239。d360),.vout_s_height(1239。d576),.vout_t_width(1239。d1024),.vout_t_height(1239。d768),.vout_K_h(1639。h005a),.vout_K_v(1639。h00c0),///////////mem .mem_clk(phy_clk),.wr_burst_req(ch1_wr_burst_req),.wr_burst_len(ch1_wr_burst_len),37.wr_burst_addr(ch1_wr_burst_addr),.wr_burst_data_req(ch1_wr_burst_data_req),.wr_burst_data(ch1_wr_burst_data),.wr_burst_finish(ch1_wr_burst_finish),.rd_burst_req(ch1_rd_burst_req),.rd_burst_len(ch1_rd_burst_len),.rd_burst_addr(ch1_rd_burst_addr),.rd_burst_data_valid(ch1_rd_burst_data_valid),.rd_burst_data(ch1_rd_burst_data),.rd_burst_finish(ch1_rd_burst_finish),.base_addr(239。d1))。//////////////////////////////////////////////////////vout_display_pro vout_display_pro_m0(.rst_n(rst_n),.dp_clk(vga_out_clk_fpga),.h_fp(H_FP[11:0]),.h_sync(H_SYNC[11:0]),.h_bp(H_BP[11:0]),.h_active(H_ACTIVE[11:0]),.h_total(H_TOTAL[11:0]),.v_fp(V_FP[11:0]),.v_sync(V_SYNC[11:0]),.v_bp(V_BP[11:0]), .v_active(V_ACTIVE[11:0]),.v_total(V_TOTAL[11:0]),.hs(vga_out_hs),.vs(vga_out_vs),.de(vga_out_de),.rgb_r(vga_out_rgb_r),.rgb_g(vga_out_rgb_g),.rgb_b(vga_out_rgb_b),.layer0_top(1239。d0),.layer0_left(1239。d0),.layer0_width(1239。d1024),.layer0_height(1239。d768),.layer0_alpha(839。hff),.layer0_rdreq(ch0_vout_rd_req),38.layer0_ycbcr(ch0_vout_ycbcr))。//////////////////////////////////////////////////////vout_display_pro vout_display_pro_m1(.rst_n(rst_n),.dp_clk(hdmi_out_clk),.h_fp(H_FP[11:0]),.h_sync(H_SYNC[11:0]),.h_bp(H_BP[11:0]),.h_active(H_ACTIVE[11:0]),.h_total(H_TOTAL[11:0]),.v_fp(V_FP[11:0]),.v_sync(V_SYNC[11:0]),.v_bp(V_BP[11:0]), .v_active(V_ACTIVE[11:0]),.v_total(V_TOTAL[11:0]),.hs(hdmi_out_hs),.vs(hdmi_out_vs),.de(hdmi_out_de),.rgb_r(hdmi_out_rgb_r),.rgb_g(hdmi_out_rgb_g),.rgb_b(hdmi_out_rgb_b),.layer0_top(1239。d0),.layer0_left(1239。d0),.layer0_width(1239。d1024),.layer0_height(1239。d768),.layer0_alpha(839。hff),.layer0_rdreq(ch1_vout_rd_req),.layer0_ycbcr(ch1_vout_ycbcr))。mem_ctrl(.MEM_DATA_BITS(MEM_DATA_BITS))mem_ctrl_m0(.rst_n(rst_n),.source_clk(clk),39.phy_clk(phy_clk),.aux_half_rate_clk(), .ch0_rd_burst_req(ch0_rd_burst_req),.ch0_rd_burst_len(ch0_rd_burst_len),.ch0_rd_burst_addr(ch0_rd_burst_addr),.ch0_rd_burst_data_valid(ch0_rd_burst_data_valid),.ch0_rd_burst_data(ch0_rd_burst_data),.ch0_rd_burst_finish(ch0_rd_burst_finish),.ch1_rd_burst_req(ch1_rd_burst_req),.ch1_rd_burst_len(ch1_rd_burst_len),.ch1_rd_burst_addr(ch1_rd_burst_addr),.ch1_rd_burst_data_valid(ch1_rd_burst_data_valid),.ch1_rd_burst_data(ch1_rd_burst_data),.ch1_rd_burst_finish(ch1_rd_burst_finish),.ch2_rd_burst_req(ch2_rd_burst_req),.ch2_rd_burst_len(ch2_rd_burst_len),.ch2_rd_burst_addr(ch2_rd_burst_addr),.ch2_rd_burst_data_valid(ch2_rd_burst_data_valid),.ch2_rd_burst_data(ch2_rd_burst_data),.ch2_rd_burst_finish(ch2_rd_burst_finish),.ch3_rd_burst_req(ch3_rd_burst_req),.ch3_rd_burst_len(ch3_rd_burst_len),.ch3_rd_burst_addr(ch3_rd_burst_addr),.ch3_rd_burst_data_valid(ch3_rd_burst_data_valid),.ch3_rd_burst_data(ch3_rd_burst_data),.ch3_rd_burst_finish(ch3_rd_burst_finish),/////////////////////////////////////////// .ch0_wr_burst_req(ch0_wr_burst_req),.ch0_wr_burst_len(ch0_wr_burst_len),.ch0_wr_burst_addr(ch0_wr_burst_addr),.ch0_wr_burst_data_req(ch0_wr_burst_data_req),.ch0_wr_burst_data(ch0_wr_burst_data),.ch0_wr_burst_finish(ch0_wr_burst_finish),.ch1_wr_burst_req(ch1_wr_burst_req),.ch1_wr_burst_len(ch1_wr_burst_len),.ch1_wr_burst_addr(ch1_wr_burst_addr),.ch1_wr_burst_data_req(ch1_wr_burst_data_req),.ch1_wr_burst_data(ch1_wr_burst_data),40.ch1_wr_burst_finish(ch1_wr_burst_finish), .ch2_wr_burst_req(ch2_wr_burst_req),.ch2_wr_burst_len(ch2_wr_burst_len),.ch2_wr_burst_addr(ch2_wr_burst_addr),.ch2_wr_burst_data_req(ch2_wr_burst_data_req),.ch2_wr_burst_data(ch2_wr_burst_data),.ch2_wr_burst_finish(ch2_wr_burst_finish),.ch3_wr_burst_req(ch3_wr_burst_req),.ch3_wr_burst_len(ch3_wr_burst_len),.ch3_wr_burst_addr(ch3_wr_burst_addr),.ch3_wr_burst_data_req(ch3_wr_burst_data_req),.ch3_wr_burst_data(ch3_wr_burst_data),.ch3_wr_burst_finish(ch3_wr_burst_finish),/////////////////////////////////////.mem_cs_n(mem_cs_n),.mem_cke(mem_cke),.mem_addr(mem_addr),.mem_ba(mem_ba),.mem_ras_n(mem_ras_n),.mem_cas_n(mem_cas_n),.mem_we_n(mem_we_n),.mem_clk(mem_clk),.mem_clk_n(mem_clk_n),.mem_dm(mem_dm),.mem_dq(mem_dq),.mem_dqs(mem_dqs),.mem_odt(mem_odt))。endmodule