畢業(yè)設(shè)計(jì)基于fpga的萬(wàn)年歷設(shè)計(jì)-資料下載頁(yè)

【導(dǎo)讀】基于FPGA的萬(wàn)年歷電路的設(shè)計(jì)

　　

【正文】 th DLL PLL. DLL used PLL and by IP core generated tools convenient to management and configuration. 7. Embedded special hardcore Embedded special hardcore is relatively lowlevel embedded soft nuclear speaking, means the FPGA processing ability strong hardcore (Core), equivalent to hardcore ASIC circuit. In order to improve the FPGA performance, chip producers in the chip inside 畢業(yè)設(shè)計(jì)（論文）專用紙 第 頁(yè) 19 integrated some special hard core. For example: in order to improve the multiplication of speed, mainstream FPGA are integrated in the FPGA special on timemultiplier。 In order to apply munications bus and interface standards, many highend FPGA internal are integrated strings and transceiver (SERDES), can achieve dozens of Gbps speed of delivery. The highend product not only Xilinx pany has integrated Power PC series CPU, still embedded with DSP Core modules, its corresponding systemlevel design tools are EDK and Platform, according to this Studio forward Chip System (System on the concept of Chip cluster generator attempts. Through Miroblaze, Picoblaze PowerPC, such as the platform, can develop standards and its associated applications DSP . The FPGA design precautions： Whether you are a logical designers, hardware engineer or system engineer, or even with all these titles, as long as you in any kind of highspeed and more plex systems use agreement the FPGA, you will probably need to resolve device configuration, power management, IP integration, signal integrity and some of the other key design issues. However, you don39。t have to face these challenges alone, because in the current leading FPGA pany application engineers every day to solve these problems, and they have put forward some amaze your design work easier design guiding principles and solutions. The I/O signal distribution Can provide the most multifunctional pins, I/O standards, termination scheme and difference right FPGA in signal distribution are the most plex design guiding principles. Although the Altera FPGA device no design guiding principles (because it realize rise pare easy), but the spirit of the FPGA design principles guiding thought is quite plex. But in either case, for I/O pins distribution, there are some signal to keep in mind is mon steps: 1. Use an electronic data list all plans signal allocation, and their important properties, such as I/O standard, voltage, need termination methods and relevant clock. 2. Check with the manufacturer block/regional patibility criteria. 畢業(yè)設(shè)計(jì)（論文）專用紙 第 頁(yè) 20 3. Consider using the second spreadsheets formulate FPGA layout to determine what tube feet is a universal, which is dedicated, which support difference signal to the and global and local clock, which need reference voltage. 4. Utilizing the above two spreadsheets information and regional patibility criterion, first distribution restricted the biggest signal to the extent the last distribution on pins, the smallest restricted. For example, you may need to distribution serial bus and the clock signal, because they usually only assigned to some special. At this stage, considering writing a contains only port distribution of HDL files. Then through the use of suppliers of tools or using a text editor manually create a limit files, for I/O standards and increase the SSO necessary support information. Ready for these basic documents, you can run layout wiring tools to confirm whether overlooked some standards or made a wrong distribution. This will make you at the initial stage design and layout engineer working together, mon planning the PCB39。s walk line, redundancy planning, heat dissipation problems and signal integrity. The FPGA tools may can provide help in these fields, and help you to solve these problems, so you must ensure that understanding your toolkit function. You consult a layout experts the later time, the more you . Based on the design of three main consumption CMOS power: internal (to short circuit), leakage (static) and switch (capacitors). When a gate transient, VDD and ground connection between internal power consumption shortcircuit. Leakage power is widespread CMOS process caused by the parasitic effect. And switch power consumption is load capacitance, discharge from the cause. Switch power consumption and short circuit power consumption together called dynamic power consumption. Underneath introduction reduce static power consumption and dynamic power design techniques. The FPGA and CPLD, the identification and classification: The FPGA and CPLD, the identification and classification is mainly according to its structure characteristics and working principle. Usually the classification method is: 畢業(yè)設(shè)計(jì)（論文）專用紙 第 頁(yè) 21 will form a structure to product the device called CPLD logical behavior, such as the Lattice of ispLSI series, Xilinx XC9500 series, Altera MAX7000S series and the Lattice (former Vantis) Mach series, etc. Will with querying method structure form logic behavior, such as Xilinx FPGA device called the SPARTAN series, Altera FLEX10K or the ACEX1K series, etc. Although the FPGA and CPLD are programmable ASIC devices, there are many mon features, but because CPLD and FPGA structural differences have respective characteristics: (1) more suitable for pleting various algorithm CPLD device logic, and the bination of FP GA is more suitable for plete temporal logic. In other words, the FPGA is more suitable for flipflop, and lots of structure is more suitable for CPLD limited and a rich trigger the structure of the product. 2 continuous type wiring structure of CPLD determines its temporal delay is uniform and predictable, and FPGA segmented wiring structure of decide their delayed unpredictability. (3) than CPLD in programming FPGA even greater flexibility. CPLD by modifying with fixed logic