基于aduc845的數據采集系統設計畢業設計-資料下載頁

【導讀】分用C語言在Keil上進行編程，使用VC編寫USB上位機程序，完成數據傳輸，系統硬件通過ADuC845內。部模數轉換模塊將從外界采集到的電壓信號經過串口RS232發送到PC機上進行實時顯示。個基于ADuC845單片機的數據采集系統的基本功能，分辨率可達到1/5000，能夠實現14位的數據輸出。該系統的采集精度大大提高，更加適用于高速度、高精度數據采集的實際工業測控。

　　

【正文】 格要求下，最終實現其預期的功能，與此同時，我也獲得了豐富的理論知識，極大地提高了自己的動手實踐能力，并對當前數據采集系統領域的研究狀況和發展方向有了一定的了解，這對我今后進一步學習數據采集方面的知識有極大的幫助。在此，我衷心感謝秦老師的悉心指導和支持。在未來的工作和學習中，我將以更好的成績來回報老師。 與此同時，我還要感謝陪伴我走過四年大學生涯的全體老師和同學門，謝謝他們一直對我的陪伴和幫助。 陜西理工學院畢業設計 第 22 頁 共 40 頁 參考文獻 [1] 莊坤領 . 基于 ADuC845 數據采集系統的研究與設計 [M].青島：中國海洋大學出版社， 20xx. [2] 李朝青 .PC 機及單片機數據通信技術 [M].北京：北京航空航天出版社， 20xx. [3] Analog Devices, AduC845/847/848 MicroCnverter Multicchannel 24 bit ADCs with embedded 62KB Flash and SingeCycle MCU. sheets/ADUC845 847 . [4] 劉敦濤，李翌，劉武 . 帶高精度 24 位 A/D 轉換的 51 核 ADuC845[M].武漢：華中師范大學， 20xx. [5] 李剛，林凌，何峰等 .ADuC845 單片機原理、開發方法及應用實例 [M].北京：電子工業出版社， 20xx. [6] 劉敦濤，李翌，劉武 . 帶高精度 24 位 A/D 轉換的 51 核 ADuC845[M].武漢：華中師范大學， 20xx. [7] 李朝青 . 單片機原理及接口技術 [M].北京：北京航空航天大學出版社， 1999. [8] 譚浩強 .C 程 序設計（第二版） .北京：清華大學出版社， 1999. [9] 謝維成 ,楊加國 .單片機原理與應用及 C51 程序設計 [M].北京：清華大學出版， 20xx. [10] 程佩清 .數字信號處理 [M].北京：清華大學出版社， 1995. [11] 王永山 ,王博 .計算機原理與應用（第三版） [M].西安：西安電子科技大學出版社， 20xx. [12]童詩白，華成英 .模擬電子技術基礎（第三版） [M].北京：高等教育出版社， 20xx. [13] 劉書明等 .數據采集系統芯片 AduCS12 原理與應用 [M].西安：西安電子科技大學出版社 ， 20xx. [14] 王福瑞 .單片微機測控系統大全 [M].北京：北京航空航天大學出版社， 1997. [15]TI MSC1210 AnologtoDigtal with 8015 Microcontroller and Flash Memeroy User’ s Guid[EB/OL], 陜西理工學院畢業設計 第 23 頁 共 40 頁 附錄 A 外文翻譯 ADuC845_847_848(3441) ADC CIRCUIT INFORMATION The AduC845 incorporates two 10channel(8channel on the MQFP package) 24bit ADCs, while the AduC847 and AduC848 each incorporate a single 10channel(8channel on the MQFP package) 24bit and 16bit. Each part also includes an onchip programmable gain amplifier and configurable buffering(neither is available on the auxiliary ADC on the AduC845). The parts also incroporate digital filtering intended for measuring wide dynamic rang and low frequencyh signals such as those in weigscale, straingage, pressure transducer, or temperature measurement applications. The ADuC845/ ADuC847/ ADuC848 can be configerd as four or five(MQFP/LFCSP package) fullydifferential input channels or as eight or ten(MQFP/LFCSP package) pseudo differential input channels referenced to AINCOM. The ADC on each part(primary only on the ADuC845) can be fully buffered internally, and can be programmed for one or eight input ranges from +20mv~20mv to +~. Buffering the input channel means that the part can handle significant source impedances on the selected analog input and that RC friltering(for noise rejection or RFI reduction) can be placed on the analog inputs. If the ADC is used with internal buffering disaled(=1,=0), these unbuffered inputs provide a dynamic load to the driving source. Therefore, resistor/capacitor binations on the inputs can impedance of the source that is driving the ADC inputs. The input channels are intended to convert aignals directly from sensors without the need for extrnal sigal condionting . With internal buffering disabled(relevant bits set/cleared in ADC0CON1), extrnal buffering might be required. When the internal buffer is enabled, it might be necessary to offset the negative input channel by +100mv and to offset the positive channel by 100mv if the reference range is Avdd. This accounts for the restricted monmode input range in the buffer. Some circuits, for example, brigde circuits, are inherently suitable to use without having to offset where the output voltage is balanced around V/2 and is not sufficiently large to encroach on the supply rails. Intenal buffering is not avalible on the auxiliary ADC(ADuC845 only). The auxiliary ADC(ADuC845) is fixed at a gain of +~. The ADCs use a conversion technique to realize up to 24 bits on the ADuC845 and the ADuC847, and up to 16 bits on the ADuC848 of no missing codes performance(20 hz update rate, chop enable). The ΣΔ modulator converts the sampled input signal into a digital pulse train whose duty cycle contains the digital information. ADC CHOPPING The ADCs on the ADuC845/ ADuC847/ ADuC848 implentend a chopping scheme where by the 陜西理工學院畢業設計 第 24 頁 共 40 頁 ADC repatedly reverses its inputs. The decimated digital outtput words from the sin3 filter, therefore, have a positive and negative offset term included. As a result, a final summing stsge is included in each ADC so that each output word from the filter is summed and averaged with the previous filter output to produce a new valid output result to be written to the ADC data SFRs. The chopping scheme incorporated into the parts results in excellent dc offset and offset drift specifications, and is externaly benefical in applications where drift, noise rejection, and optimum EMI performance are inportant. ADC chop can be disabled cia the chop bit in the ADCMODE SFR(). Setting this bit to 1(logic high) disables chop mode. CALIBRATION The ADuC845/ ADuC847 ADuC848 incorporate four calibration modes that can be progrommed via the mode bits in the ADCMODE SFR detailed.. Every part is calibrated before it leaves the factory. The resulting offset and gain calibration coefficients for both the primary and auxiliary(ADuC845 only) ADCs are stored onchip in manufacturingspecific Flash/EE memory locaions. At poweron or after a reset, these factory calibration registers are automatically downloaded to the ADC calibration registers in the part’s SFR space. To facilitate user calibration, each of the primary and auxiliary(ADuC845 only) ADCs have dedicated calibration controol SFrs, which are discribed in the ADC SFR interface section. Once a user intiates a calibration procedure, the factory calibration values that were initally downloaded during these poweron sequence to the ADC calibration SFRs are overwritten. The ADC to be calibrated must be enabled via the ADC enable bits in the