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【正文】 run a little slower. If things work out right, his clock will be more accurate. Over a series of weekly adjustments, the wall clock39。s notion of a second would agree with the reference time (within the wall clock39。s stability).An early mechanical version of a phaselocked loop was used in 1921 in the ShorttSynchronome clock.Structure and functionPhaselocked loop mechanisms may be implemented as either analog or digital circuits. Both implementations use the same basic structure. Both analog and digital PLL circuits include four basic elements:˙Phase detector,˙Lowpass filter,˙Variablefrequency oscillator, and˙feedback path (which may include a frequency divider).Performance parameters˙Type and order˙Lock range: The frequency range the PLL is able to stay locked. Mainly defined by the VCO range.˙Capture range: The frequency range the PLL is able to lockin, starting from unlocked condition. This range is usually smaller than the lock range and will depend . on phase detector.˙Loop bandwidth: Defining the speed of the control loop.˙Transient response: Like overshoot and settling time to a certain accuracy (like 50ppm).˙Steadystate errors: Like remaining phase or timing error˙Output spectrum purity: Like sidebands generated from a certain VCO tuning voltage ripple.˙Phasenoise: Defined by noise energy in a certain frequency band (like 10kHz offset from carrier). Highly dependent on VCO phasenoise, PLL bandwidth, etc.˙General parameters: Such as power consumption, supply voltage range, output amplitude, etc.ApplicationsPhaselocked loops are widely used for synchronization purposes。 in space munications for coherent demodulation and threshold extension, bit synchronization, and symbol synchronization. Phaselocked loops can also be used to demodulate frequencymodulated signals. In radio transmitters, a PLL is used to synthesize new frequencies which are a multiple of a reference frequency, with the same stability as the reference frequency.Other applications include:˙Demodulation of both FM and AM signals˙Recovery of small signals that otherwise would be lost in noise (lockin amplifier)˙Recovery of clock timing information from a data stream such as from a disk drive˙Clock multipliers in microprocessors that allow internal processor elements to run faster than external connections, while maintaining precise timing relationships˙DTMF decoders, modems, and other tone decoders, for remote control and telemunicationsClock recoverySome data streams, especially highspeed serial data streams (such as the raw stream of data from the magnetic head of a disk drive), are sent without an acpanying clock. The receiver generates a clock from an approximate frequency reference, and then phasealigns to the transitions in the data stream with a PLL. This process is referred to as clock recovery. In order for this scheme to work, the data stream must have a transition frequently enough to correct any drift in the PLL39。s oscillator. Typically, some sort of redundant encoding is used, such as 8b/10b encoding.DeskewingIf a clock is sent in parallel with data, that clock can be used to sample the data. Because the clock must be received and amplified before it can drive the flipflops which sample the data, there will be a finite, and process, temperature, and voltagedependent delay between the detected clock edge and the received data window. This delay limits the frequency at which data can be sent. One way of eliminating this delay is to include a deskew PLL on the receive side, so that the clock at each data flipflop is phasematched to the received clock. In that type of application, a special form of a PLL called a delaylocked loop (DLL) is frequently used.Clock generationMany electronic systems include processors of various sorts that operate at hundreds of megahertz. Typically, the clocks supplied to these processors e from clock generator PLLs, which multiply a lowerfrequency reference clock (usually 50 or 100MHz) up to the operating frequency of the processor. The multiplication factor can be quite large in cases where the operating frequency is multiple gigahertz and the reference crystal is just tens or hundreds of megahertz.Spread spectrumAll electronic systems emit some unwanted radio frequency energy. Various regulatory agencies (such as the FCC in the United States) put limits on the emitted energy and any interference caused by it. The emitted noise generally appears at sharp spectral peaks (usually at the operating frequency of the device, and a few harmonics). A system designer can use a spreadspectrum PLL to reduce interference with highQ receivers by spreading the energy over a larger portion of the spectrum. For example, by changing the operating frequency up and down by a small amount (about 1%), a device running at hundreds of megahertz can spread its interference evenly over a few megahertz of spectrum, which drastically reduces the amount of noise seen on broadcast FM radio channels, which have a bandwidth of several tens of kilohertz.Clock distributionTypically, the reference clock enters the chip and drives a phase locked loop (PLL), which then drives the system39。s clock distribution. The clock distribution is usually balanced so that the clock arrives at every endpoint simultaneously. One of those endpoints is the PLL39。s feedback input. The function of the PLL is to pare the distributed clock to the ining reference clock, and vary the phase and frequency of its output until the reference and feedback clocks are phase and frequency matched.PLLs are ubiquitous—they tune clocks in systems several feet across, as well as clocks in small portions of individual chips. Sometimes the reference clock may not actually be a pure clock at all, but rather a data stream with enough transitions that the PLL is able to recover a regular clock from that stream. Sometimes the reference clock is the same freq