基于時頻信號的鎖相式頻率合成器的設計與制作畢業(yè)設計報告正式-資料下載頁

【導讀】亞洲共有6個國家發(fā)播時號；它們是中國、日本、印度、印度尼西亞、斯里蘭卡和土耳其。發(fā)播時間也很短。與短波相比，長波傳播穩(wěn)定，時號的接收精度有了明顯提高。長波白天地波的覆。蓋范圍大約為1000KM，夜間天波的覆蓋范圍可達2500KM。目前，世界上最大的長波授時系統(tǒng)是美國。我國的長波授時原理和信號格式與美國的羅蘭-C系統(tǒng)相同。位于西安東北的蒲城縣境BPL長波授時臺兼導航臺。隨著科技不斷的發(fā)展電話授時、網(wǎng)絡授時是隨這國家信息事業(yè)高速發(fā)展的產(chǎn)物，是新的授時手段。同時與鎖相環(huán)結合的頻率合成技術是基于鎖相技術的頻率合成方法，目前應。它是利用鎖相環(huán)路的良好窄帶跟蹤特性，使輸出頻率準確地鎖定在高穩(wěn)定參考頻率或。其高次諧波上，使被鎖定的頻率具有與參考頻率一致的頻率穩(wěn)定度和頻譜純度。便自動接收、并進入尋常百姓家成為可能，從而將對世界經(jīng)濟的發(fā)展產(chǎn)生重大的影響。電波鐘表極為重視，紛紛采取措施，以期盡早投入使用。它的試驗臺于1980年就開始為用戶服務了。

　　

【正文】 McGRAWHILL,1984. [10]Egan,Willam F.,Frequency Synthesis by Phase Lock John Wileyamp。Sons， 1981. [11]Holmes,.,Coherent Spread Spectrum Systems, John Wileyamp。Sons， 1982. [12] , “Wahre Und Scheinbare Intensit 228。tsverteilung In Spektrallinien. II.”,. 81 (1933) 428. [13]王德凡、蘭海峰、劉佑華 .MOTOROLA大規(guī)模集成電路鎖相環(huán)頻率合成器 器件 [J].， . 陜西理工學院畢業(yè)論文（設計） 第 24 頁 共 31 頁 附錄 A 英文文獻原文 PLL Overview 出處： PLL Performance, Simulation, and Design 3rd Edition（ 110） Dean Banerjee Basic PLL Operation and Terminology This section describes basic PLL (PhaseLocked Loop) operation and introduces terminology that will be used throughout this book. The PLL starts with a stable crystal reference frequency, XTAL, which is divided down to a lower frequency by the R counter. This divided frequency is called the parison frequency (Fp) and is one of the inputs to the phase detector. The phasefrequency detector outputs a current that has an average DC value proportional to the phase error between the parison frequency and the output frequency, after it is divided by the N divider. The constant of proportionality is called K φ. This constant turns out to be the magnitude of the current that the charge pump can source or sink. Although it is technically correct to divide this term by 2π, it is unnecessary since it is canceled out by another factor of 2π which es from the VCO gain for all of the equations in this book. So technically, the units of K φ are expressed in mA/(2π radians).If one takes this average DC current value from the phase detector and multiplies it by the impedance of the loop filter, Z(s), then the input voltage to the VCO (Voltage Controlled Oscillator) can be found. The VCO is a voltage to frequency converter and has a proportionality constant of Kvco. The loop filter is a low pass filter, often implemented with discrete ponents. The loop filter is application specific, and much of this book is devoted to the loop filter. This tuning voltage adjusts the output phase of the VCO, such that its phase, when divided by N, is equal to the phase of the parison frequency. Since phase is the integral of frequency, this implies that the frequencies will also be matched, and the output frequency will be given by OUTF N XTALR??（ ） 陜西理工學院畢業(yè)論文（設計） 第 25 頁 共 31 頁 This applies only when the PLL is in the locked state。 this does not apply during the time when the PLL is acquiring a new frequency. For a given application, R is typically fixed,and the N value can easily be changed. If one assumes that N and R must be an integer, then this implies that the PLL can only generate frequencies that are a multiple of Fp. For this reason, many people think that Fp and the channel spacing are the same. Although this is often the case, this is not necessarily true. For a fractional N PLL, N is not restricted to an integer, and therefore the parison frequency can be chosen to be much larger than the channel spacing. There are also less mon cases in which the parison frequency is chosen smaller than the channel spacing to overe restrictions on the allowable values of N, due to the prescaler. In general, it is preferable to have the parison frequency as high as possible for optimum performance. Note that the term PLL technically refers to the entire system shown in Figure 。 However, sometimes it is meant to refer to the entire system except for the crystal and VCO. This is because these ponents are difficult to integrate on a PLL synthesizer chip. The transfer function from the output of the R counter to the output of the VCO determines a lot of the critical performance characteristics of the PLL. The closed loop bandwidth of this system is referred to as the loop bandwidth (Fc), which is an important parameter for both the design of the loop filter and the performance of the PLL. Note that Fc will be used to refer to the loop bandwidth in Hz and ωc will be used to refer to the loop bandwidth in radians. Another parameter, phase margin ( φ), refers to 180 degrees minus the phase of the open loop phase transfer function from the output of the R counter to the output of the VCO. The phase margin is evaluated at the frequency that is equal to the loop bandwidth. This parameter has less of an impact on performance than the loop bandwidth, but still does have a significant impact and is a measure of the stability of the system. The PLL as a Frequency Synthesizer The PLL has been around for many decades. Some of its earlier applications included keeping power generators in phase and synchronizing to the sync pulse in a TV Set. Still other applications include recovering a clock from asynchronous data and demodulating an FM modulated signal. However, the focus of this book is the use of a PLL as a frequency synthesizer. In this type of application, the PLL is used to generate a set of discrete frequencies. A good example of this is FM radio. In FM radio, the valid stations range from 88 to 108 MHz, and are spaced MHz apart. The PLL generates a frequency that is MHz less than the desired channel, since the received signal is mixed with the PLL signal to always generate an IF (Intermediate Frequency) of MHz. Therefore, the PLL generates frequencies ranging from MHz to MHz. The channel spacing would be equal to the parison frequency, which would is 100 fixed crystal frequency of 10 MHz can be divided by an R value of 100 to yield a parison frequency of 100 kHz. Then the N value ranging from 773 to 973 is programmed into the PLL. If the user is listening t